Visit Tela Innovations at DAC for details of our collaborative programs with TSMC aimed at lowering power and reducing die sizes.
PowerTrim
Reduce leakage of logic blocks by up to 50% while maintaining the area and timing of your design
AreaTrim
Reduce the area of logic blocks by 20% using co-optimized standard cell libraries compatible with your existing design flow
Presentation:
Improving Chip Quality of Results (QoR) Through Process-Design Co optimization
Monday, July 27 – 12:00-12:15 PM and 3:30-3:45 PM
Tuesday, July 28 – 4:00-4:15 PM
Wednesday , July 29 – 11:30-11:45 AM
OIP Partner Passport
Enter into the Open Innovation Platform (OIP) passport program to receive a special exhibitor gift bag from TSMC!
See Tela Innovations at the TSMC Open Innovation Platform™ partner booth #822. Learn more about how our interfaces and collaborations with TSMC create greater accuracy and quality in your designs.
Read the press release
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Monday July 27, 1:00pm - 3:00pm | Room 130
Tela’s Senior Vice President of Product Technology, Mike Smayling, will join with industry leaders to address the current state of DFM and describe tangible and specific progress in a number of design areas targeted at 45nm and below. Organized by the Si2 and the Design for Manufacturability Coalition, the workshop will present interface standards being developed between chip design and manufacturing flows.
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