Visit Tela Innovations at DAC for details of our collaborative programs with TSMC aimed at lowering power and reducing die sizes.
PowerTrim
Reduce leakage of logic blocks by up to 50% while maintaining the area and timing of your design
AreaTrim
Reduce the area of logic blocks by 20% using co-optimized standard cell libraries compatible with your existing design flow
Presentation:
Reducing Power and Area with PowerTrim and AreaTrim
Monday, June 14 - 4:00p-4:15 PM
Tuesday, June 15 – 12:00-12:15 PM
Wednesday , June 16 – 3:00-3:15 AM
OIP Partner Passport
Enter into the Open Innovation Platform (OIP) passport program to receive a special exhibitor gift bag from TSMC!
See Tela Innovations at the TSMC Open Innovation Platform™ partner booth #822. Learn more about how our interfaces and collaborations with TSMC create greater accuracy and quality in your designs.
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