Cadence, Tela present how gridded approach can be used for logic and SRAM at 20nm and beyond

Engineers from Tela and Cadence collaborated on a presentation at the 2011 SPIE Conference that showed how Tela’s unique one-directional layout technique can be applied to not just standard cells, but also SRAM. The paper, entitled “Custom Source and Mask Optimization for 20nm SRAM and Logic” discussed an approach that truly optimizes both logic and SRAM, instead of the conventional approach of sacrificing the SRAM because of logic layouts with bends and multiple pitches.

The team showed how the design with both logic and SRAMs was considered unified from the beginning. In this case, critical layer orientations as well as pitches were matched and each of the layers optimized for both functional sets of patterns. The layout for a typical standard cell used Gridded Design rules. A group of SRAM bit cells were designed to be compatible with the logic cell.

Optimization results were presented for the co-optimization of critical layers for the cells. The team showed how the Source-Mask Optimization (SMO) method used can optimize the illumination source and mask for multiple patterns to improve the 2-D image fidelity and process window while controlling the mask sensitivity. It can incorporate the design intentions that are implied by Gridded Design rules. SMO was done to balance complexity of the source and the complexity of the mask (OPC & MBSRAFs).

To download this paper in its entirety, click here.

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