Canon, TEL present findings on using Tela for 20nm and beyond at SPIE 2012

A team of engineers and researchers from Canon, Tokyo Electron (TEL), Sequoia Design Systems and Tela recently collaborated on a paper that was presented at the 2012 SPIE Lithography Conference. The paper, titled “Sub-20nm Logic Lithography Optimization with Simple OPC and Multiple Pitch Division” describes the process and results for doing a series of advanced CMOS logic designs, first with single patterning and a highly regular layout style using Gridded Design Rules (GDR). It also looks into the process of using double and triple patterning for critical layers.

The transition from single- to double- and in some cases triple- patterning was evaluated for different layout styles, with highly regular layouts delaying the need for multiple-patterning compared to complex layouts.
To address mask complexity and cost, OPC for the “cut” patterns was studied and relatively simple OPC was found to provide good quality metrics. This is significant since mask data volumes of >500GB per layer are projected for pixelated masks created by complex OPC or inverse lithography; writing times for such masks are nearly prohibitive.

The team extended the scaling using simplified OPC beyond 20nm in small steps, eventually reaching the 16nm node. The same “cut” pattern was used for each set of simulations, with “x” and “y” locations for the cuts scaled for each step. The test block was a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops.

The paper presents an experimental demonstration of the cut approach using simplified OPC and conventional illuminators and compares this to the complex OPC result. Lines were patterned with 193nm immersion with no complex OPC. The final dimensions were achieved by applying pitch division twice.

To download this paper in its entirety, click here.

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