TSMC Technology Symposium – April 9, 2013

Tuesday, April 9th
San Jose McEnery Convention Center
San Jose, CA
Booth 501

http://www.hwacomms.com/TSMC2013/NAtechsymposium/Attendee/index.html

Tela Presents Sub 12nm Results at SPIE 2013

Sub-12nm Optical Lithography with 4x Pitch Division and SMO-Lite™
— SPIE 2013
download paper >>

DAC 2013 Austin: Celebrating 50 years of Innovation

Austin, TX
The Live Music Capital of the World becomes the Electronic Design Capital of the World

Conference dates: June 2-6, 2013
Exhibition dates: June 3-5, 2013
Booth 1815

http://www.dac.com/dac+2013.aspx

TSMC Open Innovation Platform Ecosystem Forum

October 16th, 2012 (Tuesday)

San Jose Convention Center, CA
150 West San Carlos St.
San Jose, CA 95110

Booth # 305

Visit Tela Innovations at the TSMC Technology Symposium Japan – June 29, 2012

TSMC Technology Symposium Japan
Date: Friday, June 29, 2012
Location: Pan Pacific Yokohama Bay Hotel
2-3-7, Minato Mirai, Nishi-ku
Yokohama, Kanagawa, Japan 220-8543
+81-45-682-2222

Visit Tela at the Design Automation Conference (DAC) 2012 – Booth #704

DAC 2012 Moscone Center, San Francisco – June 3-7 2012
The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. Now in its 49th year, DAC features a wide array of technical presentations, as well as the leading electronics design suppliers in a colorful, well-attended trade show that, literally, attracts stakeholders from around the world.

Cadence, Tela present how gridded approach can be used for logic and SRAM at 20nm and beyond

Engineers from Tela and Cadence collaborated on a presentation at the 2011 SPIE Conference that showed how Tela’s unique one-directional layout technique can be applied to not just standard cells, but also SRAM. The paper, entitled “Custom Source and Mask Optimization for 20nm SRAM and Logic” discussed an approach that truly optimizes both logic and SRAM, instead of the conventional approach of sacrificing the SRAM because of logic layouts with bends and multiple pitches.

Paper predicts the use of regular 1D patterns can help extend CMOS logic to 7nm node

At the 2012 SPIE Conference a paper was jointly presented by Tela and engineers from Leti, the French applied research center, that showed the benefits of a highly regular layout style comprised of “lines” and “cuts”. Entitled “Sub-20nm Hybrid Lithography using Optical + Pitch-Division and e-Beam”, the paper concluded that by utilizing regular 1D patterns instead of random 2D shapes – as well as a variety of other techniques – CMOS logic can be extended to the 7nm node using existing immersion lithography.

Canon, TEL present findings on using Tela for 20nm and beyond at SPIE 2012

A team of engineers and researchers from Canon, Tokyo Electron (TEL), Sequoia Design Systems and Tela recently collaborated on a paper that was presented at the 2012 SPIE Lithography Conference. The paper, titled “Sub-20nm Logic Lithography Optimization with Simple OPC and Multiple Pitch Division” describes the process and results for doing a series of advanced CMOS logic designs, first with single patterning and a highly regular layout style using Gridded Design Rules (GDR). It also looks into the process of using double and triple patterning for critical layers.