Canon, TEL present findings on using Tela for 20nm and beyond at SPIE 2012

A team of engineers and researchers from Canon, Tokyo Electron (TEL), Sequoia Design Systems and Tela recently collaborated on a paper that was presented at the 2012 SPIE Lithography Conference. The paper, titled “Sub-20nm Logic Lithography Optimization with Simple OPC and Multiple Pitch Division” describes the process and results for doing a series of advanced CMOS logic designs, first with single patterning and a highly regular layout style using Gridded Design Rules (GDR). It also looks into the process of using double and triple patterning for critical layers.

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