TSMC aiming for more than financial returns with its investment in US start-up Tela Innovations

Taiwan Semiconductor (TSMC), the world’s leading microchip foundry company, will invest $65 million in California-based start-up Tela Innovations through its venture capital arm TSMC Partners.

Founded in 2005, the US company is seen as one of the brightest prospects in electronic design automation (EDA) technology for the semiconductor industry, having already gained investment from key chip players Intel, Qualcomm, Cadence and KLA-Tencor.

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TSMC invests in EDA David that slew Google

TSMC invests in EDA David that slew Google Leading foundry Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan) has said it intends to invest about $65 million in EDA startup Tela Innovations Inc. (Los Gatos, Calif.).

The investment is being made through TSMC Partners, according to a Digitimes report that referenced a company filing with the Taiwan Stock Exchange as its source.

Read more at: eetimes.com

TSMC to invest in Tela for US$65 million

Jessie Shen, DIGITIMES

TSMC Partners, a TSMC unit engaged in making investments in semiconductor companies, will buy about 10 million shares of Tela Innovations for US$6.24 a share or a total of US$65 million, according to a company filing with the Taiwan Stock Exchange (TSE).

The transaction will enable TSMC Partners to hold a 25% stake in Tela, the filing disclosed.

In February 2009, TSMC and Tela formed a strategic partnership to develop co-optimized design solutions using Tela’s patented lithography-optimized design technology and TSMC’s derivative processes.

read full article here: digitimes.com

Taiwan Semiconductor Manufacturing subsidiary to invest in Tela Innovations


Taiwan Semiconductor Manufacturing Co Ltd:Subsidiary TSMC Partners, Ltd. to acquire 10,420,868 shares of Tela Innovations, Inc. at $6.24 per share with amount of $65 million.TSMC Partners, Ltd. to hold ,420,868 shares (25 pct stake) of Tela Innovations, Inc. after investment.

Read more at: Reuters

Tela Named one of Top 10 Tech Start-ups to Watch in 2013

by Peter Clarke

Processors, memory, manufacturing processes, chip architecture, EDA, MEMS, RF, touch screens, servers and the Internet of Things are markets where startups can still make a difference.

What follows are ten rising companies worth tracking in 2013.

Tela Innovations

Tela Innovations Inc. (Los Gatos, Calif.) was founded in 2005 and started by working with Qualcomm on computational lithography with a view to the extraction of multi mask information for the double patterning era.

Tela’s technology is delivered as physical design representation applied to standard cell logic and embedded SRAM, analog and I/O that can result in area savings and reduced leakage current. The company offers gate-length trade-offs for power, performance and area within its libraries. Tela has also specialized in working with customers’ IP development teams to get the technology into production.

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Cell libraries optimized for 32/28nm and 22/20nm mfg

EDN Asia

Tela Innovations has released its new standard cell libraries optimized for 32/28nm and 22/20nm manufacturing processes. The foundry-independent libraries leverage the company’s proactive approach to the design challenges posed by lithography constraints at 28nm and below, stated the company.

The Tela approach embraces the inherent lithography constraints and results in designs with simpler, more manufacturable shapes. From a designer’s perspective, Tela’s approach to layout is transparent, as the libraries contain a complete set of functions that provide the ability to implement optimized designs based on all of their specific performance, power and area (PPA) requirements. In addition, the Tela libraries go further and introduce cell options for routability tradeoffs providing additional design flexibility, the company revealed.

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Startup rolls complementary litho

EE Times, Mark LaPedus

SAN JOSE, Calif. – At the SPIE Advanced Lithography conference here, maskless startup Multibeam Corp. will outline more details about its ongoing efforts to commercialize its so-called Complementary E-Beam Lithography (CEBL) technology in the market.

Multibeam (Santa Clara, Calif.) will describe the latest developments of its CEBL tool, a multi-column, maskless lithography system designed for patterning the most critical layers in a design–contact holes, vias and line cutting–at the 16-nm node and beyond. Throughput is said to be five wafers an hour–more than twice the speed of today’s single-beam e-beam tools.

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ML2 Lithography: One Tool to Write Them All

Semiconductor Manufacturing and Design
By Marc D. Levenson

Does the transition to 450mm wafers offer the ultimate opportunity to switch to maskless lithography (ML2)? That was the suggestion made by Burn Lin, senior director of micropatterning at TSMC in his keynote for the SPIE Alternative Lithography Conference in San Jose Feb. 14. The 450mm transition would appear to require expensive development of a variety of patterning tools and resists if a conventional mix-and-match strategy were employed. Since multi-electron beam lithography can be used to write any layer, one 450mm e-beam direct-write tool could pattern them all, and for 30% lower cost at any production volume. Only one machine would have to be engineered and only a few resists formulated.

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eBeam Initiative SPIE 2012 Luminaries Dinner – Mike Smayling, Tela Innovations

The eBeam Initiative held its annual Luminaries Dinner at the Plumed Horse Restaurant in Saratoga, CA. This exclusive event gathers the industry’s top minds after a day at the 2012 SPIE Advanced Lithography Conference.

Tela Innovations – 1D Layout is Good For DFM

by Daniel Payne in Cell Libraries, DAC 2009

Neal Carney met with me on Monday afternoon to provide an update on what’s new at this hard IP company. They acquired Blaze DFM in the last year and are offering two products: PowerTrim and AreaTrim.TSMC is their exclusive partner using these new 1D layout cells that provide improved performance and yield at 65nm nodes and smaller.With PowerTrim the idea is to look at your design after placement and routing, find all the paths that still have margin and then selectively upsize the channel lengths to reduce power consumption while maintaining timing specs. Users benefit as these updated cells have reduced leakage because of the CD biasing. In one example I saw a 42% reduction in leakage current while only increasing the path delay by 7%.

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