Cell libraries optimized for 32/28nm and 22/20nm mfg

EDN Asia

Tela Innovations has released its new standard cell libraries optimized for 32/28nm and 22/20nm manufacturing processes. The foundry-independent libraries leverage the company’s proactive approach to the design challenges posed by lithography constraints at 28nm and below, stated the company.

The Tela approach embraces the inherent lithography constraints and results in designs with simpler, more manufacturable shapes. From a designer’s perspective, Tela’s approach to layout is transparent, as the libraries contain a complete set of functions that provide the ability to implement optimized designs based on all of their specific performance, power and area (PPA) requirements. In addition, the Tela libraries go further and introduce cell options for routability tradeoffs providing additional design flexibility, the company revealed.

The 32/28nm libraries are available in architectures optimized for density or speed, and support poly-silicon gate as well as high-K metal gate, gate first and gate last, processes. They come with a complete set of logic and storage elements with multiple circuit variants, including drive strengths and parametric tradeoffs, as well as specialized cells to implement arithmetic and register file functions. The libraries support traditional back-end, physical EDA views including GDSII, schematics and circuit simulation.

The libraries are capable of supporting Tela’s gate length biasing technology while maintaining maximum layout pattern uniformity. Gate length biasing techniques provide a significantly better leakage vs. speed tradeoff option for designers compared to multiVt techniques, added the company.

For 22/20nm libraries, the absence of a new generation of lithography such as EUV introduces new challenges. Printing 20nm features with 193nm light requires new design approaches encompassing not only Restricted Design Rules (RDR) but double patterning compatible layout as well. The introduction of double patterning for metal layers and local interconnects creates additional complexities for chip designers. Tela’s layout in its 22/20nm library ensures the cleanest pattern splitting, resulting in highly manufacturable patterns on the masks, the company indicated. These libraries also incorporate innovative circuit and layout design techniques to maximize the benefit of new process features such as local interconnect.

These new libraries are available from Tela. Due to the more simplified architecture of these libraries, they can also be quickly customized to specific customer requirements.

http://www.ednasia.com/ARTP_8800505878_1000005.HTM

© Copyright Tela Innovations, Inc. - Theme by Pexeto