Tela Innovations’ focus is to innovate in the area of physical IC design to enable improved optimization of IC manufacturing processes. Unlike many Design for Manufacturing (DFM) approaches that look to “fix” a design Tela is focused on creating a design methodology upfront that is highly manufacturable in a given lithography system. With the recent acquisition of Blaze-DFM, Inc. Tela adds new patented capabilities to optimize designs to improve power consumption. A unifying theme of Tela’s approach is close collaboration with manufacturers to achieve optimum results. This is evidenced by the recently announced strategic relationship with the world’s largest foundry, Taiwan Semiconductor Manufacturing Company (TSMC).

Tela’s technology is broadly applicable to both existing and future process nodes. Tela’s Power Optimization capability is being applied to nodes from 90nm down to 40nm with plans to extend it to 32nm and below. Tela’s Layout Optimization capability is applicable to nodes from 180nm down to 32nm. At 32nm and below, it becomes increasingly difficult to resolve critical features sizes with single exposure, 193nm lithography systems. This drives the need for double patterning approaches. Tela’s straight line, 1D layout style can greatly simply the fracturing of design data to enable double patterning making Tela a key enabling technology for the future. The chart below shows what lithography capability is required at each logic node in terms of k1 and the fact that 1D features are easier to resolve than conventional 2D. The subsequent chart shows an example of how Flash memory devices, which are essentially designed using 1D features have achieved better density and smaller area than logic which has historically utilized 2D layout structures.