Tela is addressing a fundamental challenge in the scaling of semiconductor technology to keep pace with Moore’s Law. Our solution is focused on the emerging manufacturing issues related to the ‘sub wavelength’ era (when features being patterned are smaller than the wavelength of the illumination light source). In the past, advancements in lithography have enabled chip design and manufacturing to scale. Today, at 45nm and beyond, lithography has reached its practical limits and scaling cannot happen without changes in design approaches. This has profound impact on chip designers, equipment manufacturers and process manufacturers.

The Tela solution introduces a new approach that uses gridded, straight line, one dimensional layout structures that produce logic blocks with a lower k₁ lithography limit. By restricting the number and type of interactions between shapes, it helps overcome the limitations of current lithography techniques. The Tela solution is an unobtrusive and effective approach to reducing variability, performance, leakage and area.

The Tela solution is aimed at advanced process geometries – 45nm and beyond – where the physical effects of chip design are most severe and complex. It is applicable for use in logic, embedded memory, analog and I/O functions. When synthesized and routed as part of the overall design, the solution enables a lithography-optimized layout. It works within standard EDA and physical design methodologies, and effectively ‘masks the physics’ from designers for a streamlined implementation model.

Tela was founded in 2005 by a team of experts in semiconductor IP, design automation and process technology. The company has been working with a set of lead customers to develop and test the solution. Early results have demonstrated as much as a 15% improvement in area and a 2.5x reduction in leakage by using the Tela solution at 45nm.

It is well-funded by well-known venture firms, including Intel Capital, the investment arm of Intel Corporation.