TELA Innovations

FAQs

What is the challenge that Telas solution is addressing?
Tela is focused on the emerging manufacturing issues related to the sub wavelength era, when features being patterned are smaller than the wavelength of the illumination light source. In the past, advancements in lithography have enabled chip design and manufacturing to scale. Today, at 45nm and beyond, lithography has reached some practical limits and scaling cannot happen without changes in design approaches.
Arent advancements in lithography, such as EUV, addressing many of these concerns?
Extreme ultraviolet light techniques hold promise but may not be commercially available for several years. With chip companies already moving to 45nm and with roadmaps to move to 32nm, a solution is required today to bridge the gap and maintain the pace of Moores Law.
What is the general concept behind your approach?
Tela offers a solution based on on-grid, straight-line, one-dimensional layout structures to produce a lithography-optimized layout. There are many examples in the industry particularly in memory applications where the storage element (DRAM cell, NAND Flash cell or SRAM cell) have been optimally laid out with lithography considerations in mind and have achieved higher density on the same manufacturing equipment. Tela has taken this approach and applied it to logic circuits and demonstrated that key SoC elements, including standard cell logic, memory periphery circuits and I/O can be implemented without sacrificing area or performance. Indeed the resulting regular structures of Telas implementation exhibit dramatically reduced variation resulting in improved performance and lower leakage. Specifically it enables patterns on a single mask to be efficiently and predictably separated into two masks, called double patterning.
What are the specific benefits of the Tela solution, in terms leakage, performance, design time, etc?
The key benefits of the Tela solution are a reduction in die area and a reduction in variability resulting in improved performance and lower leakage. Area reduction is achieved though a combination of Telas proprietary layout techniques and in optimizing the OPC algorithms and design rules to reflect the fixed, regular nature of Telas implementation. With relatively minor optimization we are seeing 10-15% smaller logic block areas. These results are post timing driven place and route results using actual customer netlists with comparable route utilization rates.
In terms of variability reduction Tela provides two benefits, first reducing device level variability but improving the uniformity of the gate length critical dimension (CD) across the width of the transistor. This is due to the straight line nature of Telas architecture. Further variation reduction is achieved by reducing context dependant variation which arises from the surrounding lithographic neighborhood in which a device is placed. With Tela not only is the cell level neighborhood uniform but the block level is as well, making the placement dependency negligible as shown in the block level view below.

This reduction in variability can translate into improvements in both performance and leakage. Telas simulations show a leakage reduction in excess of 2.5 times that of a conventional layout.
What technology node are you targeting for adoption of your approach?
There are advantages to be gained in terms of lowering variation that result in dramatic reductions in leakage of over 2.5X at 45nm that are compelling even without extensive optimization of existing 45nm design rules and process flows. At 32nm, with process and design rules still being finalized, there is an opportunity to co-optimize the design and process to extract the maximum capability from a 32nm capital equipment investment. At 22nm and beyond the physics dictate that the design methodology needs to change toward more regular structures in order to enable techniques like double patterning to be deployed.
What is the advantage or need for double patterning?
Double patterning refers to techniques that separate a single very dense pattern into two lower resolution patterns and printing them in separate passes. The two separate mask patterns would be aligned and interlaced to in order to produce the desired high density pattern on the actual wafer. This approach requires very precise alignment or overlay tolerances on the printing of the two masks but lowers the resolution required to print the individual masks. The need for double patterning techniques is driven by reaching the physical limits of the dimensions that can be resolved with current light sources and lenses. The equipment suppliers are working to improve overlay accuracy and wafer throughput to make double patterning economically feasible.
An additional challenge to deployment of double patterning is in creating physical design layouts that can be easily split and optimized that maintain competitive area and electrical performance characteristics. Telas on-grid, single orientation straight line architecture accomplishes this.
What kind of circuit elements does this apply to?
Telas initial focus is on applying its solution to standard cell logic followed by embedded SRAM memories, analog and I/O.
What is the difference between this approach and restricted design rules?
The chart below from an AMD presentation shows the complexity IC designers are dealing with. It is interesting to note the logarithmic scale this is plotted on showing the exponential increase in volume and complexity of design rules. Restricted Design Rules (RDR) in contrast to the implication of the word Restriction only increase the complexity of what designers need to deal with. RDRs are typically added to this already complex set of rules and introduce conditional sets of rules. Simplistically this might look like - If this shape is next to this type shape then the spacing needs to be Y instead of X.
Tela uses a small set of deterministic rules to implement a fixed set of patterns or topologies that are used to build circuit functions. The net result for blocks implemented with Telas approach is a regular pattern across the entire block. Another way of viewing Telas approach is that it tells a design what to do vs. a either a traditional design rule or RDR approach which tells a designer what not to do.
What impact does this have on a traditional design methodology? Arent you just introducing yet another tool or step for already overburdened designers to have to deal with?
Actually, the Tela solution reduces the burden for designers in terms of thinking about DFM (design for manufacturability). The Tela solution is delivered as a physical design representation (GDSII) of a customers design IP. When synthesized and routed as part of the overall design, the solution enables a lithography-optimized layout. It works within standard EDA and physical design methodologies, and effectively hides the physics from designers for a streamlined implementation model.
What impact does this have on the targeted manufacturing processes? What kind of relationship do you need with the manufacturers to implement this?
Telas solution can be applied to existing foundry processes and rules. More optimum results can be achieved through collaboration with the manufacturers on Optical Proximity Correction (OPC) algorithms and on sets of rules that are applicable to Telas structures.
What impact does this have on equipment manufacturers?
Equipment manufacturers also realize that design style has a major impact on what types of process steps are feasible to implement. Tela presented joint papers at the SPIE Advanced Lithography Conference with ASML and Applied Materials presenting results of how Telas design approach helped enable new process techniques to be implemented. Increasingly design, equipment and process technology will need to be co-optimized to continue the scaling of semiconductors.
What level of silicon results have you seen with your technology?
We have run test chips with our structures through a leading manufacturer and have seen good results. Additional test chips are in fab now at 45nm with another manufacturer with more planned with additional companies over the next 6 months.
Are you engaged with any customers yet?
Yes, we are currently engaged with significant fabless, foundry and IDM customers. Qualcomm has been an early engagement customer for us providing excellent feedback to us as noted in the press release. We cannot be specific on additional companies we are working with but will announce them at the appropriate time. In addition we are working closely with equipment manufacturers, foundries, and EDA tool suppliers to enable an ecosystem of support for this new approach.
Given that this approach is based a very regular method, is it difficult to patent? Have you applied for any patents?
Over the past three years of working on this approach Tela has developed a number of innovations that result in a very efficient implementation of its architecture. Building a patent portfolio around these innovations is a key part of our strategy and we have a number of applications in various stages of review.
What is your business model do you license tools? IP?
Telas strategy is to partner with customers IP development teams to enable the solution to be adopted and deployed for production IC design. Since each of these customers has unique requirements there is a customization or services component to each engagement. Tela will deliver physical design information (GDSII) to our customers as part of these engagements as well as tools to support and automate the deployment of Tela based IP. It is Telas intention to license both our IP and tools to customers as part of these engagements.