DOD SILICON VALIDATION
Department of Defense Silicon Validation
Working with the DoD, Tela has validated the following:
- 1D layout can be used to re-implement 2D circuits with no area penalty with same design rules
- 1D layout can be used to re-implement 2D circuits with no performance penalty with the same Spice models
- 1D layout of standard cells and memories can be automated
- Use of 1D layout can be supported by standard EDA design flows
90nm 1D Validation Test Chip
Below are the results of a DARPA funded 90nm test-chip. A logic block was implemented with DoD supplied 2D standard cells and with Tela 1D standard cells. The silicon results show that Tela’s 1D layout created a smaller, faster and better yielding logic block than the 2D layout.
The results of Tela’s 1D implementation were:
- 20% smaller
- 25% faster
- 30% better yield
45nm SOI Radiation Hard By Design (RHBD) Validation Test Chip
Below are the results of a DARPA and DTRA funded 45nm SOI test-chip. A logic block design was implemented with DoD supplied 2D standard cells and Tela 1D standard cells. The DICE DFF cells provide radiation hardness by design (RHBD). The 1D and 2D libraries have the same cell list and are based on the same Spice netlist. The 1D+ library contains additional cells to improve area and performance.
Note that the 1D+ implementation with DICE DFF cells is smaller than the 2D implementation without DICE DFF, thus eliminating the area, performance and power, penalty associated with 2D RHBD.
- Block with DICE using Tela 1D+ is 30% smaller than block with DICE using 2D
- Block with DICE using Tela 1D is 8% smaller than non-DICE using 2D
- Tela 1D/1D+ provides equivalent radiation hardness and soft-error robustness as 2D