Layout optimization startup Tela buys Blaze DFM

Dylan McGrath
EETimes
2/24/2009 2:00 AM EST
http://eetimes.com/electronics-news/4081456/Layout-optimization-startup-Tela-buys-Blaze-DFM

SAN FRANCISCO—Blaze DFM, the design-for-manufacturing-focused startup that was reputed to have closed its doors last December, has been acquired by fellow startup Tela Innovations. Financial details were not disclosed.

Tela (San Jose, Calif.) also announced a strategic partnership with No. 1 semiconductor foundry Taiwan Semiconductor Manufacturing Co. (TSMC) Ltd. around Tela’s lithography-optimized design technology. Tela executives said the deal is similar to the 2008 agreement between Blaze and TSMC that launched the foundry’s PowerTrim service. Tela said it intends to continue supporting the PowerTrim service.

Tela said it would work jointly with TSMC to integrate is design technology, which emphasizes layout optimization, with TSMC’s process technology to optimize designs for power, performance and area. The deal makes available certain elements of Tela’s technology to TSMC on an exclusive basis, the company said.

“To do this type of optimization really requires a very close working relationship,” said Neal Carney, vice president of marketing at Tela. “We have to be very careful that as we gain exposure to their process technology it doesn’t get spilled over to their competitors.”

Carney said Tela is involved in ongoing discussions with other potential customers but was not ready to disclose any additional relationships at this time.

Carney and Scott Becker, Tela’s president and CEO, said the acquisition of Blaze made since because of several synergies between the two companies, including close relationships with TSMC and the fact that both companies’ technologies support design and process co-optimization.

The Tela solution uses fixed, pre-defined physical topologies on a global basis to implement logic design that is optimum for the lithography used in a given process, while the Blaze technology provides a capability to further optimize each transistor of a design to achieve timing and power objectives, they said.

“Really it’s about built-in DFM optimization,” Carney said.

Tela emerged last year to unveil computational lithography technology that addresses the challenges of fabricating chips at the 45-nm and below, basing its approach on on-grid, straight line, one- dimensional layout structures. Tela, founded in 2005, is privately funded by several venture capital firms and boasts former Cadence Design Systems Inc. executives Ray Bingham and Jim Hogan on its board of directors.

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