ML2 Lithography: One Tool to Write Them All

Semiconductor Manufacturing and Design
By Marc D. Levenson

Does the transition to 450mm wafers offer the ultimate opportunity to switch to maskless lithography (ML2)? That was the suggestion made by Burn Lin, senior director of micropatterning at TSMC in his keynote for the SPIE Alternative Lithography Conference in San Jose Feb. 14. The 450mm transition would appear to require expensive development of a variety of patterning tools and resists if a conventional mix-and-match strategy were employed. Since multi-electron beam lithography can be used to write any layer, one 450mm e-beam direct-write tool could pattern them all, and for 30% lower cost at any production volume. Only one machine would have to be engineered and only a few resists formulated.

The architecture of Lin’s tool would be similar to a multi-column version of KLA-Tencor’s ReBL system, with several wafers on a rotating stage and up to 36 columns, each supporting one million independent beams. Direct write with continuous stage motion on all levels would allow devices to break out of the standard 26 x 33mm field, with consequent efficiency improvements. The issue, as always in electron beam lithography, would be throughput. Lin claimed that could be addressed by scaling the number of columns and stages. Mass production would reduce tool cost to $500,000 per wafer per hour. Lin claimed that by the time 450mm came along, the CD would be 10nm or below, making his suggested ML2 architecture the least challenging and most economical of the available options.

Other advocates of ML2 and alternative lithographies seemed less visionary. The KLA-Tencor presentations on ReBL emphasized the steps needed to re-target the DARPA-funded 45nm program towards commercial viability at 16nm or so in 2015. Regina Freed described how returning to linear stage motion reduced risk and complexity with the lower stage velocity needed for 1nm CDU and overlay at 16nm. There still could be 36 columns and the throughput target would be 100 wph.

Mark McCord of KLA-Tencor described the hardware evolution towards high-volume manufacturing (HVM). Going to linear stages simplified the data channel, allowing re-use of data, but still required a 6 Gb/s channel for each column. The key element of the reflective million pixel design is the Digital Pixel Generator (DPG), which consists of a 248×4096 CMOS shift register underlying a 1.6mm MEMS electron lens array. McCord showed that the first CMOS chips are now working, producing a checkerboard pattern that was focused onto the wafer plane and scrolled at stage speed to facilitate time domain integration (TDI) of the exposure. At designed demagnification, the pixels would be 6nm and edges would be placed to <1nm by using 31 different dose levels. If all goes well, a TDI-exposed wafer would appear soon, and the end of 2012 would see a 100kV 100X demagnification machine with 4 wafers and four 4th generation columns working simultaneously to yield 4-8 wafers/hour using 30mC/cm2 resist. E- Beam Initiative

At the annual E-Beam Initiative lunch Managing Director Aki Fujimura noted that his organization is an educational platform for all electron-beam applications with 42 member companies, and open to all. In 2012, he predicted that the design for e-beam program (DFeB) would demonstrate mask-CD uniformity improvement on the first full-chip model based mask data preparation (MB-MDP) example. Ryan Pearman of D2S described how MB-MDF facilitated the use of overlapping circular shots to draw curved and diagonal mask features with better edge definition and uniformity. Both shot count and edge placement errors are reduced when circles replace rectangles stitched together at corners, according to Pearman.

Mike Smayling of Tela Technologies described how e-beam lithography could be used for the tiny and difficult “cut” operations in proposed 11nm complimentary lithography. In this system, proposed by Yan Borodowski of Intel and already being used by that company, all circuit features begin as linear and uniform line-and-space gratings. The gratings are then cut into useful circuit elements by subsequent exposures. The problem has been that up to 5 additional optical exposures would be needed to make all necessary circuit geometries because of the fundamental ~80nm limit on the minimum resolved pitch of each optical exposure.

Complementary Lithography process with 193nm immersion lithography. Different colors denote each of the 4 cut-mask exposures. (Courtesy Intel)

Smayling pointed out that an e-beam system could write all of the cuts at once, using Tela’s patented system, which would be much faster than writing the entire pattern. No e-beam system has yet been optimized for this specialized application, but he showed an example of an 11nm grating with cuts made using a Vistec electron lithography system at Cea-Leti .

Later in the conference, Kenji Abe described more esthetic 22nm and 11nm line-and-cut results achieved on a multi-column cell projection prototype by a team from eBI member Advantest and TEL. In the first stage, the line grating was written by TEL’s self aligned double or quadruple patterning process.

Then one beam of the Advantest MCC-POC EdBW tool cut line ends with 5nm overlay accuracy using either a positive or negative tone process. Development etching and subsequent processing resulted in controllable line end spacings down to 13nm. Abe pointed out that such a tool could cut the gate and M1 patterns anticipated for the 11nm node. Other papers from Advantest recommended design and resist innovations that would facilitate EbDW with character projection. The goal is 100 WPH at the 14nm node in a 150 beam, 10 cluster system with 100B shots/wafer, and 75mC/cm2 resist. The drastic shot reduction required may first prove feasible in complementary lithography.

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