PATENTED INNOVATIONS FROM TELA
The team at Tela Innovations has extensive experience developing novel approaches to the design challenges at advanced technology nodes. Tela has developed technology that addresses the design constraints resulting from the lithography challenges of moving to 32nm and smaller geometries. An overview of the technology Tela has developed is provided in the table below.
The development of solutions to these design challenges by the engineers at Tela has resulted in an extensive portfolio of patents that are available for licensing to companies in the semiconductor and electronics industry. A listing of Tela’s U.S. patents is available from the U.S. Patent and Trademark Office (USPTO) website here.
| Examples of Tela’s Innovations | Benefits | |
| Design with linear gate electrode level segments | Linear gate electrode level segments | Extend lithography capability for gate layer |
| Dummy gates | Pattern uniformity – manufacturability | |
| Gates on a fixed pitch | Pattern uniformity – transistor variability | |
| Contact placement | Optimum interconnect usage | |
| Linear interconnect segments | Extend lithography capability for metal layers | |
| Mux and latch implementation | Area and performace | |
| Combinational logic implementation | Area and performace | |
| Mux and latch implementation where both internal mux and feedback transistor gate cross connections are made in levels other than the gate level | Gates on a fixed pitch | Pattern uniformity – transitor variability |
| Location of gate level contacts | Optimum interconnect usage | |
| Optimum gate electrode placement | Mux and latch configuration for a variety of uses such as memories and cell based logic | |
| Dummy gates | Pattern uniformity – manufacturability | |
| Linear interconnect segments | Extend lithography capability for metal layers | |
| Interfacing cells and blocks implemented with linear gate electrode level segments | Maintain gate electrode level uniformity across boundaries | Pattern uniformity – transistor variabilty and chip manufacturability |
| Design with Local Interconnect | Linear local interconnect with linear gate level segments | Density and manufacturability of designs |
| Low Power | Gate length biasing | Fine grained speed-power optimization |
| Annotation layer to implement gate length biasing | Optimum bias communication from design to manufacturing | |
