Physical IP
Tela offers Physical IP products for ASIC and SoC designs that address the design challenges of restricted design rules in advanced technology nodes. Tela has developed an extensive set of standard cell libraries based on it’s patented layout approach. In addition, Tela has implemented SRAM and I/O functions in this novel layout style and offers customization services to port customers’ IP to this physical design implementation. learn more >>

Power Optimization
Tela also offers unique solutions to power reduction through patented Gate Length Biasing technology and an advanced optimizer software tool that has proven to provide best-in-class results vs. other EDA solutions. Access to this capability is offered through either a design service engagement or software license model. Tela’s proprietary Gate Length Biasing technology is available through TSMC. learn more >>

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