Leakage-Delay Optimization Techniques
The power consumed by leakage currents in advanced process nodes has become a large portion of the overall power budget and has driven designers to employ multiple techniques to reduce leakage power in the digital logic portion of complex SoC ASIC designs. The graph above shows the impact that different implants can have on the threshold voltage of devices and the resulting impact on sub-threshold or source-drain leakage. To take advantage of this, standard cell library variants with multiple threshold transistors can be used to insert slower, lower leakage cells on non-critical paths. Multi-Vt libraries provide a fairly “coarse” set of trade-offs in that there are large delay penalties for large reductions in leakage.
More recently, varying the gate length of transistors in standard cell libraries has emerged as an additional technique to provide more, finer grained choices of cells with different leakage-delay trade-offs. As shown in the graph above there is an exponential relationship between source-drain leakage and gate length but only a linear impact on the delay. In addition, transistor gate lengths can be varied in small increments thereby providing more fine-grained trade-offs between leakage and delay. This can result in the ability to swap many more lower leakage cells on non-critical paths resulting in significantly lower leakage with no impact to overall speed of the IC. Speed is not impacted because no cells are swapped on critical paths.
Varying the gate length of standard cell libraries is accomplished in two ways. Cells can be designed with longer than minimum channel length transistors. The cells of this library variant would be slower and lower leakage. Within the same footprint of these longer channel length cells, minimum gate length cells can be used to create faster, higher leakage cells. Since the cells have the same footprint, they can be swapped on non-critical paths just as cells with different Vt’s can be swapped. This methodology has an area impact as the longer gate length cells have a larger footprint than they otherwise would have if minimum gate lengths had been used.
In addition to the above method of varying the gate length, a technique called gate length biasing (GLB) is also used to provide incremental gate length changes. Gate length biased cells typically are the same area as the base or nominal cell and therefore share the same footprint enabling them to be swappable. GLB library variants are characterized for delay and leakage characteristics associated with the gate lengths that will be manufactured. The actual physical gate length biasing occurs post tape out. Gate length biased transistors are marked with a layer in the GDSII database and are identified for either increases or decreases as part of the mask fabrication process. In this manner, transistors in a complex SoC ASIC can be biased selectively and by varying amounts.
With emergence of these multiple techniques to optimize designs for leakage and delay, it is important that the design flow and optimization tools select the most appropriate cells to produce the best quality of results. As can be seen in the graph above, there can be cell choices that are sub-optimal. Circled above are examples where a longer gate length is always better than a shorter channel, higher Vt choice. Coupled with the fact that each additional Vt results in incremental masks and process steps, and their associated costs, it is imperative that the optimization flow makes correct choices, not only from a parametric quality of results point of view but from a die cost perspective as well.
Given that Vt cell swapping was the first technique to become mainstream in advanced technology node design flows, there is the potential that some flows and tools have embedded algorithms that favor Vt swapping or swap Vt cells first. As shown above, this may not produce optimal results. Tela Innovations’ optimizer was developed with a fine grained algorithm from the start and has demonstrated superior results on over 50 production tape outs to date.
For more information on Tela’s optimizer and design optimization services click here.