Tela offers two differentiated solutions in the leakage power optimization arena: the industry-leading Tela Optimizer tool and patented gate-length biasing technology. Each can be used independently. Each can deliver very significant reductions in leakage power on the standard cell portions of semiconductor chips.
Tela’s gate-length biasing technology has been used successfully on over 100 designs that are in volume production. The gate-length biasing technology is licensed to TSMC and is available to customers through TSMC. Several customers have adopted this solution and implemented multiple generations of their designs using this technology to control leakage and leakage variability.
Power Optimization Software – Tela Optimizer
The Tela Optimizer is a high-performance optimizer featuring a built-in static timing engine and can perform a full multi-mode, multi-corner (MMMC) leakage power optimization to reduce standard cell leakage power without sacrificing chip speed. To maximize leakage savings the optimization is typically performed after timing closure (or as close to it as possible). The optimizer performs cell-swapping based on available libraries and supports Gate Length Biased (GLB), Multi-Vt, and Multi-Channel cells. Because of Tela’s superior optimization technology, standard cell leakage power reductions of 25-80% have been achieved on designs that have already been optimized using Industry EDA tools and in-house optimization scripts.
The table above shows the impact of using both gate length biasing and the Tela Optimizer on designs that had employed Multi-Vt libraries or a combination of Multi-Vt and Multi-Channel libraries.
The table below highlights the quality of results (QoR) that the Tela Optimizer alone can have on designs. This table demonstrates the ability of the software to improve the QoR using the same set of libraries, showing a head to head comparison of the Tela Optimizer vs. EDA industry tools.