POWER OPTIMIZATION

TSMC PowerTrim™

Tela has licensed its patented gate length biasing technology to TSMC. The table below lists the TSMC process nodes that currently support gate length biasing. Access to this technology is provided by TSMC through its PowerTrim program for nodes from 90nm down to 40nm. The 28nm nodes listed below offer both positive and negative gate length biasing thereby increasing customers flexibility to optimize the speed and leakage power of their logic designs.