POWER OPTIMIZATION


Variability and Yield

In advanced process technologies not only has the magnitude of leakage current increased but the variability of leakage currents from lot to lot in manufacturing have also dramatically increased. As gate lengths have decreased, small variations in line edge roughness of the actual physical gate on the chip become a higher percentage of the average gate length across the width of the transistor. These variations are amplified by the exponential relationship between gate length and leakage current. Substituting gates with longer channel lengths on non-critical paths not only reduces leakage on that path but also reduces leakage variability from lot to lot.

The illustration above is based on customers’ measurements of leakage current on identical designs before and after Tela performed optimization using longer channel length, gate-length biased cells. In these cases customers had data from multiple lots, across multiple process corners for the before and after comparison. The only difference in the design was the poly gate mask that implemented the gate biasing. The key result for these customers was not only the improvement in the mean leakage but the dramatic increase in yield to their worst case leakage test limit. More and more end customers are demanding a guarantee on power consumption resulting in a requirement for this type parametric test limit for Iddq.

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