TECHNICAL PAPERS


To download the following Technical papers, please register, or if you have already registered, then click here.

Sub-12nm Optical Lithography with 4x Pitch Division and SMO-Lite™
— SPIE 2013

Sub-20nm Logic Lithography Optimization with Simple OPC and Multiple Pitch Division
— SPIE 2012

Sub-20nm Hybrid Lithography using Optical + Pitch-Division and e- Beam
— SPIE 2012

Custom Source and Mask Optimization for 20nm SRAM and Logic
— SPIE 2011

Optical lithography applied to 20nm CMOS Logic and SRAM
— SPIE 2011

Supreme lithographic performance by simple mask layout based on lithography and layout co-optimization
— SPIE 2011

Joint-Optimization of Layout and Litho for SRAM and Logic towards the 20 nm node, using 193i
— SPIE 2011

E-Beam to Complement Optical Lithography for 1D Layouts
— SPIE 2011

16nm with 193nm Immersion Lithography and Double Exposure
— SPIE 2010

22nm Logic Lithography in the Presence of Local Interconnect
— SPIE 2010

Joint-Optimization for SRAM and Logic for 28nm node and below
— SPIE 2010

Inter-layer Self-Aligning Process for 22nm Logic
— SPIE 2010

32nm and below Logic Patterning using Optimized Illumination and Double Patterning
— FEBRUARY 2009

Gridded Design: Rules – 1-D Approach Enables Scaling of CMOS Logic
— Nanochip Technology Journal – Issue Two 2008

Design Automation Conference Presentation
— June 2008 — DAC

APF Pitch-Halving for 22nm Logic Cells using Gridded Design Rules
— February 2008 — SPIE Advanced Lithography

Low-k1 Logic Design using Gridded Design Rules
— February 2008 — SPIE Advanced Lithography

DFM-It’s About Flexibility
— April 2007 — EDP Conference

© Copyright Tela Innovations, Inc. - Theme by Pexeto