Current approaches to lithography have reached their practical limits at process technologies of 45nm and beyond. This is a result of some fundamental issues with the physics behind the wavelength of light and numerical aperture, both of which began to create issues in design and manufacturing around the .65nm process. New design and manufacturing approaches are required to maintain the pace of Moore’s Law, approaches. But these approaches must not increase the complexity of design. Tela’s mission is to offer a way to “mask the physics” and still provide a solution that can effectively enable manufacturable and predictable designs in the sub-wavelength, low k 1 era.

In order to overcome lithography limitations designers and manufacturers are moving to double patterning (DP) and double exposure (DE) techniques. Tela’s solution simplifies the path to DE and DP and makes it easy to split layouts (masks) for DE and DP.

It does this by using pre-defined physical topologies, applicable for use in logic, embedded memory, analog and I/O functions. These topologies are designed to limit the number and type of interactions with shapes in a design, However, unlike traditional design rules – which tell a designer what not to do - Tela’s gridded, straight line, one dimensional layout structures effectively guide a designer on what to do to ensure a more manufacturable design. This results in a more predictable logic block pattern that is also correctable. A designer can utilize as few as 100 topologies instead of adhering to thousands of design rules which often times conflict with one another.

Tela’s solution consists of IP and tools to enable a 1-dimensional design “canvas.” The redefined topologies have fixed pitches and widths, have a single orientation with straight lines, and have no bends, jogs or shoulders. The structure can be easily split for double patterning.

From a design perspective, the use of Tela’s solution is straightforward and integrates with most popular EDA-based methodologies. It supports efficient layout and timing generation and there is no need for the designer to touch a transistor.

The Tela solution is delivered as a physical design representation (GDSII) of a customer’s design IP. Tela’s initial focus is on applying its solution to standard cell logic followed by embedded SRAM memories, analog and I/O. The nature of Tela’s solution leads to increased levels of automation for IP development which will be delivered through an Authoring System tool. This tool will enable developers to proliferate IP that conforms to the Tela physical architecture.