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• 16nm with 193nm Immersion Lithography and Double Exposure
  SPIE 2010
   
• 22nm Logic Lithography in the Presence of Local Interconnect
  SPIE 2010
   
• Joint-Optimization for SRAM and Logic for 28nm node and below
  SPIE 2010
   
• Inter-layer Self-Aligning Process for 22nm Logic
  SPIE 2010
   
• 32nm and below Logic Patterning using Optimized Illumination and Double Patterning
  SPIE Advanced Lithography Conference — February 2009
   
• Gridded Design: Rules - 1-D Approach Enables Scaling of CMOS Logic
  Nanochip Technology Journal — Issue Two 2008
   
• Design Automation Conference Presentation
  DAC - June 2008
   
• APF® Pitch-Halving for 22nm Logic Cells using Gridded Design Rules
  SPIE Advanced Lithography -— February 2008
   
• Low k₁ Logic Design using Gridded Design Rules
  SPIE Advanced Lithography — February 2008
   
• DFM – It’s all about Flexibility
  EDP Conference — April 2007