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• APF® Pitch-Halving for 22nm Logic Cells using Gridded Design Rules
  Michael C. Smayling^a, Christopher Bencherb, Hao D. Chen^b, Huixiong Dai^b, Michael P. Duane^b
  a-Tela Innovations, Inc., 655 Technology Pkwy, Suite 150, Campbell, CA, USA 95008
  b- Applied Materials, Inc., 3050 Bowers Ave., Santa Clara, CA, USA 95054
  
  The 22nm logic technology node with dimensions of ~32nm will be the first node to require some form of pitch-halving. A unique combination of a Producer APF-based process sequence and GDR-based design style permits implementation of random logic functions with regular layout patterns. The APF (Advanced Patterning Film) pitch-halving approach is a classic Self-Aligned Double Patterning scheme (SADP) [1,2,3,4] which involves the creation of CVD dielectric spacers on an APF sacrificial template and using the spacers as a hardmask for line frequency doubling.The Tela Canvas^TM implements Gridded Design Rules (GDR) using straight lines placed on a regular grid. Logic functions can be implemented using lines on a half-pitch with gaps at selected locations.
  February 2008 — SPIE Advanced Lithography
  
   
• Low k₁ Logic Design using Gridded Design Rules
  Michael C. Smayling^a, Hua-yu Liub, Lynn Cai^b
  a-Tela Innovations, Inc., 655 Technology Pkwy, Suite 150, Campbell, CA, USA 95008
  b-ASML Brion Technologies, 4211 Burton Dr., Santa Clara, CA USA 95054
  
  Dimensions for 32nm generation logic are expected to be ~45nm. Even with high NA scanners, the k₁ factor is below 0.32. Gridded-design-rules (GDR) are a form of restricted design rules (RDR) and have a number of benefits from design through fabrication. The combination of rules and topologies can be verified during logic technology development, much as is done with memories. Topologies which have been preverified can be used to implement random logic functions with hotspot prevention that is virtually context-independent. Mask data preparation is simplified with less aggressive OPC, resulting in shorter fracturing, writing, and inspection times. In the wafer fab, photolithography, etch, and CMP are more controllable because of the grating-like patterns. Tela Canvas^TM GDR layout was found to give smaller area cells than a conventional 2D layout style. Variability and context independence were also improved.
  February 2008 — SPIE Advanced Lithography
  
   
• DFM – It’s all about Flexibility
  Michael C. Smayling, Tela Innovations, Campbell, CA, mike@tela-inc.com
  
  The semiconductor industry has made great progress during the past 50 years, loosely following a trend described as Moores Law in a continual drive for lower cost per function. Design for Manufacturability (DFM) has been an integral part of sustaining the trend, contrary to the belief that DFM was recently invented by a horde of EDA startups. The necessity for true DFM is discussed in the context of the current industry move to the 45nm logic technology node. Photolithographic fidelity, limited by the cost and availability of advanced scanners, requires extensive post design processing or drives a change in design style.
  April 2007 — EDP Conference