TELA INNOVATIONS SHOWCASES DESIGN AND PROCESS CO-OPTIMIZATION SOLUTIONS AT 2009 DAC

Expanded offering addresses power and area reduction through tight connection to TSMC manufacturing process

SAN JOSE, Calif. – July 13, 2009 – Tela Innovations, which provides design solutions to enable continued cost-effective scaling of semiconductor manufacturing, will be demonstrating advancements in both its straight-line, one dimensional layout optimization technology and its CD biasing technology for reducing power at the 46th annual Design Automation Conference (DAC) July 26-30 in San Francisco. Both technologies work in conjunction with underlying manufacturing process technologies to optimize for critical area and power requirements. The company, which acquired the power optimization solution from Blaze Technology earlier this year, will demonstrate the results of its continued collaboration with TSMC in tightly coupling it design technology with the foundry’s advanced manufacturing processes.

Tela’s technology will be on display at both its own booth (#710) as well as in TSMC’s Open Innovation Platform booth (#822).

Tela has worked closely with TSMC on developing the PowerTrim service, which uses its patented technology to reduce leakage power by as much as 50% in the logic portion of chip designs. It employs an innovative technique involving gate length biasing to optimize leakage power consumption while maintaining the original area footprint and performance of the design. The exclusive PowerTrim service provides TSMC customers with a unique solution that blends Tela’s design technology with specially tuned advanced semiconductor processes to improve power consumption.

Similarly, the two companies are working together on leveraging Tela’s fixed, pre-defined physical topologies to implement logic designs that are optimum for the lithography used in a given process. They will be offering products under a program called AreaTrim, across a range of TSMC’s process technologies from 180nm to 40nm. The offering for TSMC customers will take advantage of Tela’s layout optimization technology combined with TSMC process technology to reduce logic area by approximately 20% depending upon process node and library.

For more information or to request a meeting at DAC please visit http://www.tela-inc.com/DAC2009.php

About Tela
Tela Innovations is a privately-held company based in Campbell, California that provides solutions addressing the challenge of scaling semiconductor design and manufacturing to advanced process nodes. The company’s solution uses gridded, straight line, one dimensional layout structures to provide a more efficient and reliable way to implement next generation chips. Tela’s pre-defined physical topologies are applicable for use in logic, embedded memory, analog and I/O. The solution provides improvements in variability, performance, leakage and area without significant impact on existing design methodologies, equipment sets or process technologies. With the acquisition of Blaze DFM in early 2009 Tela added power optimization technology to its line up deploying its patented gate CD biasing technology to reduce leakage power. Tela was founded in 2005 by a team of experts in semiconductor IP, design automation and process technology, and is backed by a number of venture firms and corporate investors, including Intel Capital, Cadence Design Systems, KT Venture Group, LLC, the investment partner of KLA-Tencor Corporation, and Qualcomm Incorporated. For more information on the company visit www.tela-inc.com.

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