Quick turnaround analysis of logic designs using power optimization technologies that have demonstrated up to 78% leakage power reduction

LOS GATOS, Calif. – June 4, 2012 – Tela Innovations, which provides design solutions to enable continued cost-effective scaling of semiconductor manufacturing, today announced the availability of a free, customized leakage analysis service for the logic portion of advanced System on Chip (SoC), ASIC designs. Reducing power to extend battery life and reduce heat dissipation is key to adding value in the highly competitive semiconductor market. The company uses a combination of its Tela Optimizer power reduction tool and its unique gate length biasing techniques to achieve up to 78% reduction in leakage on designs that have already been optimized using industry standard EDA tools and in-house optimization scripts.

The analysis capability is part of a new web site Tela launched today, that includes a range of enhanced information on the company’s technology, including in-depth presentations on key power and area saving techniques, as well as a comprehensive set of technical papers addressing the design challenges of advanced manufacturing nodes. There is also information on actual production silicon leakage improvement results across different technology nodes and block sizes.

“We have seen excellent results using our Tela Optimizer tool and proprietary gate length biasing approach on a variety of design types and process nodes that use a combination of Multi-Vt and Multi-Channel Length cells, with improvements of more than 50% being typical,” said Scott Becker, president and CEO of Tela. “Even in cases where the same libraries are used, our tool alone has demonstrated leakage reduction of more than 30% compared to optimizations done with traditional EDA solutions. We are looking forward to having design engineers see what we can do for their specific designs with this new analysis capability we are offering through our web site.”

Simple analysis form to complete
Design engineers can fill out a simple form that requests some basic information about a design, such as the process node, number of standard cell instances, primary clock frequency, mix of Vt’s used, as well as leakage information from their current designs.

Based on the information provided, Tela will provide an estimate of leakage reduction based on its tool and database of previous design optimizations it has done. Results can be received within two business days of submission of the design information. Customers interested in implementing this solution into their design can either engage in a design service mode, with Tela doing the optimization or they can license the software and integrate it into their sign-off design flow.

The Tela Optimizer is a high-performance optimizer featuring a built-in static timing engine and can perform a full multi-mode, multi-corner (MMMC) leakage power optimization to reduce standard cell leakage power without sacrificing chip speed. To maximize leakage savings the optimization is typically performed after timing closure (or as close to it as possible). The optimizer performs cell swapping based on available libraries and supports Gate Length Biased (GLB), Multi-Vt, and Multi-Channel cells.

About Tela
Tela Innovations is a privately-held company based in Los Gatos, California that provides solutions addressing the challenge of scaling semiconductor design and manufacturing to advanced process nodes. Tela was founded in 2005 by a team of experts in semiconductor IP, design automation and process technology, and is backed by a number of venture firms and corporate investors, including Intel Capital, Cadence Design Systems, KT Venture Group, LLC, the investment partner of KLA-Tencor Corporation, and Qualcomm Incorporated. For more information on the company visit

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