Overview
The era of sub-wavelength lithography, where features sizes are smaller than the wavelength of light used to resolve them presents many challenges to manufacturers trying to maintain the economic scaling of semiconductors postulated by Moore’s Law. These techniques include optical proximity correction (OPC) and a broad category of techniques described as design for manufacturing (DFM). Tela has taken a different approach by examining design approaches in the context of what the lithography capability can support and creating physical design structures and layouts that are optimized for a given lithography system. The key innovations are maintaining customers’ design intent, preserving existing design flows and methodologies while implementing a fixed number of highly regular, pre-determined layout topologies that can be optimized for manufacturing. The industry has numerous examples of where more regular, fixed structures can achieve improved density and performance vs. more unconstrained random layout approaches. Two examples are in Flash memory structures and SRAM bit cells where the same lithography equipment is being used to print much more aggressive feature sizes than the corresponding logic node. While logic must implement a much more varied set of functions than memories, these same principles can be applied to logic design to achieve impressive results in terms of area improvement and reduction in device variability.

Characteristics of Tela Layout
Tela has chosen to implement its patented technology initially within a standard cell methodology that is supported by extensive investments in tools and design flows at customers. This time-tested methodology has delivered a well accepted balance between design productivity and quality of results (performance and area). The figure below is an example of Tela’s layout style embodied in one widely used standard cell.

Example of Scan D Flip Flop (SDFF) Cell

• Fixed pitch, single orientation, straight line poly-silicon layer
  The printing and formation of the poly-silicon layer is key to device characteristics and device variability. Tela’s regular poly structures enable process optimization for improved area and device characteristics.
   
• Predictable Poly – Diffusion interaction
  Conventional layout using a set of design rules can result in an infinite number of possible shape interactions making it difficult to optimize or model these interactions precisely. Tela uses a small, finite number of pre-determined structures that can be optimized and modeled accurately. Accurate modeling removes variability and uncertainty from the design resulting in less design margin being required to hit performance and parametric yield targets.
   
• Options for 1D and 2D metal
  Tela’s technology can be deployed on the front end of line (FEOL) process steps of IC manufacturing which focus on device fabrication. In addition it can also be applied to back end of line (BEOL) process steps where 1D metal interconnect can be patterned using more regular structures increasing interconnect density and virtually eliminating so called manufacturing hot spots. Significant benefits can be realized from deployment on FEOL steps in the process and using conventional design rule based metal interconnects.
   

Benefits of Tela’s Technology

• Lower cost
  Enabling design and process co-optimization results in smaller die area. 1D structures can be printed with tighter pitches compressing area. 20% smaller standard cell area has been achieved with process optimization. Customers can see improvements in cost per function and manufacturers can see more efficient use of their large fixed asset base of expensive manufacturing equipment.
   
• Improved performance
  Printing 1D shapes can be accomplished with higher fidelity than complex 2D patterns. This increased fidelity translates into less variability in device performance. While improved device variability has many benefits a key one for today’s portable, battery operated products is a reduction in leakage power. Poly critical dimensions (CD) can be more precisely controlled with 1D shape having a direct impact on leakage. Ioff varies exponentially with gate length and any shortening of the gate length across the width of a transistor will increase leakage. Tela has measured a 50% reduction in drain - source leakage on a 45nm LP process in test silicon.
   

45nm LP Test Chip Data