Tela power optimization software performs a comprehensive power and timing optimization of a finished design just prior to the handoff to manufacturing. No changes to any of the design layers are made during this optimization. Instead, the software outputs an annotation layer in the handoff GDSII database that gives detailed guidance to the OPC flow used in manufacturing.

Reducing Leakage with Gate Length CD Biasing
The Tela power optimization software uses a patented technique to selectively increase or bias the gate lengths of transistors in a design with the objective of reducing leakage. Its powerful timing optimization engine analyzes timing paths in a design identifying non-critical paths that can be biased with small increases in gate lengths to save power. With Ioff varying exponentially with gate length and Ion varying linearly the net result of gate CD biasing is a significant reduction in leakage with minimal impact to timing. Since only a small percentage of paths in a design are timing critical leakage power reductions of up to 50% on the logic portion of designs are achievable. This reduction is on top of other leakage optimization techniques including the use of multi-Vt libraries and low leakage processes.

Up to 50% leakage power reduction on logic
No impact to chip area or performance

Patented Gate CD Biasing Methodology