Overview
The TSMC PowerTrim Service takes advantage of the exponential relationship between gate length and source drain leakage enabling small increases or biases in gate length to significantly reduce leakage power. Give that Ion has a linear relationship with gate length and is proportional to speed, these small biases in gate length have minimal impact on a designs performance and can be applied to transistors that are not on timing critical paths. Tela’s optimization software can analyze designs, and intelligently apply these gate length biases to the appropriate devices in a tape out ready design to reduce leakage or standby power as much as 50% without impacting the timing of the design. This reduction is in addition to other leakage mitigation techniques such as the use of multi Vt libraries and low leakage processes.

Maintaining the Area Footprint of the Original Design
As depicted below, there are multiple gate CD biases supported by TSMC. These biases are implemented as part of the OPC flow by annotating the original design with marker layers for each bias condition used. This allows the customer to tape out their original GDSII with no changes. TSMC’s pre-approved support for these gate length bias means there is no impact to the chip area.

PowerTrim Service Flow
A high level view of the PowerTrim Service is depicted below. Customers provide details of their design through a questionnaire that enables TSMC to provide an estimate of the power reduction that can be achieved. If this level of reduction is of interest to the customer they can proceed toward tape out of the design and enter into a service engagement to have the final design go through the PowerTrim optimization and timing signoff. This involves analyzing the design, applying biases and doing post optimization timing signoff with the customer. At this point in the flow it is possible to run prototype silicon comparing the original design to the PowerTrim optimized design or move straight to production with the optimized design.